Current implementation • ZenOS 1.1.0 • September 2026

ZenOS RTOS

A compact ARM Cortex-M RTOS with a bitmap-based priority scheduler, statically sized task resources, bounded IPC, runtime monitoring and configurable safety mechanisms.

Implementation-first documentation. This page describes the current source-tree behavior. It does not imply IEC certification, product compliance, benchmark guarantees or that every safety mechanism is enabled by default.

Scheduler & priorities

  • Default: 16 priority slots.
  • Configurable range: 2..256 slots.
  • Priority 0 is reserved for idle and is not an application priority.
  • At 256 slots, application priorities are 1..255; larger numeric values have higher priority.
  • Ready selection uses a bitmap and per-priority ready queues; selection scans the configured priority range.
  • Supporting 256 slots does not allocate a fixed 256-task table.

Timing

  • Default kernel tick: 100 µs.
  • Configurable range: 100..1000 µs, subject to the source validation rules.
  • Periodic tasks use period_ticks and next_run_time as a scheduler release gate.
  • Short microsecond delays are busy-wait operations; blocking delays yield the CPU.

Static resources

  • Default stack request: 128 bytes; task creation enforces an effective minimum allocation of 256 bytes.
  • Custom task stack sizes are available through os_task_create_st().
  • The kernel task model uses statically sized task resources rather than a general-purpose task heap.
  • Peak stack usage should be measured on the final target build.

IPC

  • Events with ISR-safe signaling where provided.
  • Mutexes with IPC ceiling behavior.
  • Compile-time bounded FIFO queues.
  • Counting semaphores.
  • ISR-safe variants should be used from interrupt context where provided.

Monitoring

  • Stack usage and watermark reporting.
  • CPU usage reporting.
  • Optional deadline monitoring.
  • Optional TCB integrity checking.
  • Fixed-size RAM error logging when enabled.

Configurable safety

  • Software and hardware watchdog integration.
  • MPU protection on suitable Cortex-M targets.
  • RAM integrity testing.
  • CRC-based integrity checking.
  • Critical-section diagnostics.
  • Safety target profiles perform compile-time configuration checks; they are not certification evidence.

Configuration defaults and limits

OptionDefaultAllowed values / limit
OS_KERNEL_TICK_PERIOD_US100 µs100..1000 µs; must divide 1000 evenly
OS_KERNEL_DEFAULT_STACK_SIZE128 B requestrequest ≥64 B; effective allocation floor 256 B; no explicit source max
OS_KERNEL_MAX_PRIORITIES16 slots2..256 slots; priority 0 idle; application 1..N-1, up to 1..255
OS_KERNEL_TICKLESS_IDLE_EN10 or 1
OS_IPC_TOOLS_EN10 or 1
OS_MONITORING_EN00 or 1
OS_MONITORING_DEADLINE_ACTION10..2
OS_MONITORING_ERROR_LOG_SIZE16≥1 entry
OS_SAFETY_*_EN00 or 1; MPU/CRC/IWDG require matching hardware
OS_SAFETY_TASK_MAX_RECOVERY3≥0
OS_SAFETY_SOFT_WDG_TIMEOUT_MS3000 ms≥0 ms; application/process safety time constrains useful value
OS_SAFETY_MAX_CRITICAL_US1000 µs≥0 µs; 0 disables check
OS_TARGET_MEDICAL_CLASS00..3
OS_TARGET_INDUSTRIAL_SIL00..4

These are source-defined defaults and limits; derived hardware capability macros are not user-configurable.

Priority scaling

SlotsApplication prioritiesQueue-head storageBitmap storage
161..1564 B requested queue-heads*4 B bitmap
321..31128 B4 B
641..63256 B8 B
1281..127512 B16 B
2561..2551024 B32 B

These figures describe derived priority-extension storage; the base implementation also keeps a 32-entry queue-head array. They are scheduler storage figures only, not total application RAM.

Read the detailed references: